1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device and, more particularly, to a contact hole of a semiconductor device and its forming method constituted by selectively etching an insulating layer to provide the contact hole with double slopes.
2. Discussion of Related Art
As a rule, a process of forming the metal line in a device such as DRAM is constituted by providing a cap structure of the metal line (conductive layer/nitride layer) and forming a sidewall by way of deposition/etching step of the nitride layer, with the cap structure and the sidewall being used as an etching-resistant layer in forming a contact hole, which process is termed SAC (Self Aligned Contact).
A conventional method of forming a contact hole of a semiconductor device will be described below in connection with the attached drawings.
FIGS. 1a-1f are cross-sectional views illustrating the formation of a contact hole making use of the SAC according to prior art.
As shown in FIG. 1a, a conductive layer 12 for forming a lower line is first formed on a semiconductor substrate 11, followed by forming a first nitride layer 13 on the conductive layer 12.
Next, a photo resist overlies the first nitride layer 13 and undergoes exposure and development, patterned into a first mask pattern 14.
As shown in FIG. 1b, using the first mask pattern 14 as a mask, the first nitride layer 13 and the conductive layer 12 are selectively etched to form a first nitride layer pattern 13a and a lower line 12a.
As shown in FIG. 1c, following removal of the first mask pattern 14, a second nitride layer 15 is formed on the whole surface of the semiconductor substrate 11 including the first nitride pattern 13a and the lower line 12a.
As shown in FIG. 1d, the second nitride layer 15 is etched back, forming a second nitride layer sidewall 15a on both sides of the first nitride layer pattern 13a and the lower line 12a.
As shown in FIG. 1e, a planarizing insulating layer 16 is formed by the SOG (Spin On Glass) on the whole surface of the semiconductor substrate 11 including the lower line 12a encompassed with cap layers such as the second nitride side wall 15a and the first nitride layer pattern 13a.
A photo resist overlies the planarizing insulating layer 16, followed by exposure and development, forming a second mask pattern 17.
A contact hole 18 is then formed by conducting the SAC, making use of the second mask pattern 17 as a mask, as illustrated in FIG. 1.
Such as in the prior art above described, the process of forming a contact hole by the SAC of a semiconductor device uses a nitride layer as an etching-resistant layer on the surface of and on the lateral sides of the lower line 12a.
In order to have a high etching selective ratio, it is preferable to thicken the nitride layer which is used as a cap layer for preventing short-circuits between the lines.
Though not shown in the figures, the subsequent process is constituted by providing a conductive plug inside the contact hole and forming the upper line which is electrically connected to the lower line via the conductive plug.
However, such a conventional process of forming a contact hole of a semiconductor device involves some problems as follows:
First, an increase in the thickness of the nitride layer used as a cap layer for encompassing the conductive material increases the period of time for the process, and the increased thickness of the nitride layer at the edge of the metal line in the SAC process limits the reduction of the design rules.
Secondly, the cap layer is needed to encompass the conductive material, resulting in an increase in the time and costs required for the entire process.